percent of the hardware every time the chip is reset.
Mobile users will appreciate the power-saving features built into all Pentiums rated at 75MHz and faster. The fully static 3.3 volt BiCMOS technology allows the processor to sleep and conserve energy while it is idle. The built-in System Management Mode power management technology allows the processor to control various system components for maximum energy savings. Two processor packaging options are available for notebook and subnotebook class machines.
Multi-processor users are well supported. Integrated into the chip is a multiprocessor interrupt controller that will support up to 16 processors for high-end applications. Intel's symmetric multiprocessing model is compatible with operating systems such as Windows NT, OS/2, and new UNIX implementations.
The Pentium requires a good motherboard to reach its full potential. Long term benchmark testing confirms the core logic chip set and L2 cache are crucial to maximum performance. As of this writing, Intel's Triton chip set is the current performance leader. It is targeted at enhancing graphics and multimedia performance in desktop systems.
Unlike its predecessors, the Triton chip set does not support memory parity checking. This is odd because Intel is the motivating force behind the PCI* interface. PCI strongly encourages parity checking and the Pentium itself is heavily parity checked. Intel Tech Support confirmed these details on parity checking and chip set workings. Currently, the Triton chip set data books are available only through non-disclosure agreements.
Intel publications state that parity checking is not necessary for the desktop environment. They support this claim with numerous statistics about memory having a mean-time-before-failure of up to 25 years. Intel took a similar statistical posture with their initial handling of the Pentium math bug. They cited a failure rate of one error out of nine billion possible divides. However, statistics are meaningless when your system has an error. Then, the rate of failure is 100 percent.
The industry's move toward non-parity checked memory is potentially far more hazardous to your data than the math bug. The Pentium could make minuscule errors only in floating point division. However, memory errors can damage any integer math function or address calculation. For example, a single undetected hot bit in a 32-bit memory location could be as devastating as 2+2 = 1,073,741,828. If the same bit becomes involved in an address calculation, the system will fail. When DOS goes out in the weeds, it crashes with a solid lock up. Windows may give a GPF*, if you're lucky. Without error detection, your corrupted data will go undetected.
Other Chip Sets
Intel offers other chip sets targeted at different audiences. The Neptune chip set is a viable option for what Intel Tech Support calls a more robust system. It supports parity checking, very large memory capacity and multiprocessing. Using desktop benchmarks, Neptune is only marginally slower than Triton.
Hot on Intel's heels are new core logic sets from other major vendors. OPTi offers its Viper chip set in both desktop and mobile versions. The Viper is highly tuned core logic with a focus on multimedia enhancements. It also supports memory parity checking. Similar to the Triton, it contains a true 64 bit memory controller supporting Extended Data Out (EDO) memory and pipelined burst cache. The chip set improves system performance by using posted writes to main memory. This frees the CPU* from waiting until the memory cycle completes. Additional enhancements like Plug and Play support, Type F DMA* for fast audio access, and IDE Mode 4* transfer rates are built-in.
Memory components are crucial to system performance. L2 SRAM* caches can be either synchronous (burst) or asynchronous (standard) designs. Pipelined synchronous SRAMs are less expensive than their standard BiCMOS synchronous counterparts. The faster synchronous SRAMs require 9ns ratings to operate with the 66MHz processor bus. Asynchronous types